1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more specifically to a memory device and the process of manufacturing such a device.
2. Description of the Prior Art
An electrically erasable programmable read only memory (EEPROM) cell is a nonvolatile writable and erasable memory cell which requires very low operating currents. The unit cell of an EEPROM may be formed by connecting a memory transistor in series with a select transistor. Some EEPROM designs are integrated so that the features of the two transistors are merged. Flash EEPROMs describe a family of single-transistor cell EEPROMs. Cell sizes of Flash EEPROMs are about half that of two transistor EEPROMs.
Flash memory designs differ in their cell structure based on whether they require one or several transistors per cell. Single-transistor self-aligned stacked-gate cells are well known. However, the single-transistor cell suffers from the possibility of over-erasure and consequent current leakage. A split-gate cell provides the equivalent of a two-transistor architecture, but requires only a little more chip area than a single transistor cell. Through a diffusion process, the split-gate creates a phantom transistor that looks like a series transistor. This allows the cell to be isolated from others in a column.
FIG. 1 shows a cross sectional elevation view of a conventional flash memory device at 10, the memory device including: a first memory cell 12 and a second memory cell 14 formed over a substrate 16, each of the cells sharing a common source region 18; and first and second drain regions 19 and 20 formed in the substrate 16 on opposite sides of the common source region 18. The first and second memory cells 12 and 14 include a first select gate stack 22 and a second select gate stack 24 respectively, each of the select gate stacks 22 and 24 having: a tunnel oxide layer 26 formed over the substrate; a first conductive layer 28 formed over the tunnel oxide layer 26 and providing a select gate of the respective memory cell; and a first dielectric layer 30 formed over the first conductive layer 26; a first spacer 32 formed adjacent an outer sidewall of the corresponding stack 22; and a second spacer 33 formed adjacent an inner sidewall of the corresponding stack 22.
Each memory cells 12 and 14 also include first and second floating gates 40 and 42 respectively. Each of the floating gates 40 and 42 including: a first portion formed over an outer portion of the common source region 18; a second portion formed superjacent an area of the substrate disposed between the common source region 18 and the corresponding one of the select gate stacks 22 and 24; and a third portion disposed over an inner portion of the corresponding one of the select gate stacks 22 and 24. A dielectric layer 44 is formed over the first and second drain regions 19 and 20, the first and second select gate stacks 22 and 24, the first and second floating gates 40 and 42, and the common source region 18. The first and second memory cells 12 and 14 further include first and second control gates 48 and 50 respectively, each of the control gates being formed over portions of the dielectric layer 44 which overly a portion of the corresponding one of the floating gates 40 and 42, and a portion of the corresponding one of the select gate stacks 22 and 24.
There are several problems associated with the manufacturing and performance of the prior art flash memory device 10. One disadvantage associated with the device 10 is that a relatively large area is required for fabricating each of the memory cells 12 and 14 on a semiconductor substrate, and therefore it is difficult to achieve very large scale integration of integrated circuits having such devices. Another disadvantage is that even though the memory cells 12 and 14 share a common source region 18, the separate control gates 48 and 50 of the two memory cells 12 and 14 must be individually selected by a decoding means (not shown). Therefore, device performance suffers. A further problem associated with the prior art flash memory device 10 is that it is difficult to control the fabrication process or the device because of the overlapping of the outer portion of the floating gates 40 and 42 over the inner portions of the first and second select gate stacks 20 and 24. Certain lithography steps required to form the device 10 are difficult to control to a degree of accuracy required to avoid shifting on the selective positions of the overlapping pairs of floating gates 40 and 42 as well as select gate stacks 22 and 24. Such shifting of the selective positions of the overlapping floating gates and select gates can effect performance of the device 10.
Fukumoto (U.S. Pat. No. 5,753,953, issued May 19, 1998) discloses a semiconductor storage device having a drain region and a source region formed in a silicon substrate, a select gate formed on the substrate between the source and drain regions, and a gate insulating film sandwiched between the select gate and substrate. On one side of the select gate, a floating-gate is formed out of a sidewall formed with an insulating film sandwiched. On the floating-gate and the select gate, a control gate is formed with an insulating film sandwiched. The insulating film directly below the floating-gate is formed as a tunnel oxide film which allows FN tunneling of electrons. In an erase operation, electrons are injected into the floating-gate from the silicon substrate, and in a write operation, electrons are extracted from the floating-gate to the drain region. A current required for writing and erasing each cell can be decreased, a low power supply can be used, and the lifetime of the tunnel insulating film can be increased. One disadvantage associated with the device described by Fukumoto is that adjacent memory cells have separate control gates which must be individually selected by a decoding means (not shown).
It is an object of the present invention to provide a flash semiconductor memory device including a pair of memory cells sharing a common source region, wherein both of the cells may be controlled by a common control gate.
It is another object of the present invention to provide a flash semiconductor memory device including a pair of memory cells sharing a common source region, wherein the amount of space required to fabricate the device on a semiconductor substrate is minimized.
It is a further object of the present invention to provide a process for manufacturing a flash semiconductor memory device including a pair of memory cells sharing a common source region, wherein the manufacturing process is easily controlled.
Briefly, a presently preferred embodiment of the present invention provides a memory device including a first memory cell and a second memory cell both controlled by a common control gate. The device includes: a substrate; a first stack and a second stack, each of the stacks including an insulating layer formed over the substrate, a first conductive layer formed over the insulating layer, and a first dielectric layer formed over the first conductive layer, each of the first and second stacks also including an inner sidewall and an outer sidewall, the inner sidewalls of the first and second stacks opposing each other and being separated by a common area of the substrate, the first conductive layers of the first and second stacks providing select gates of the first and second memory cells respectively, the inner and outer sidewalls of the first and second select gate stacks being coated with a second dielectric layer; first and second spacers are formed adjacent the portions of the second dielectric layer that are coated on the inner sidewalls of the first and second stacks respectively, the first and second spacers being separated by a medial portion of the common source area of the substrate, each of the spacers including a tunnel oxide layer disposed over the substrate, and a second conductive layer disposed over the tunnel oxide layer, the second conductive layers of the first and second spacers providing first and second floating gates of the first and second memory cells respectively, first and second drain regions are formed in the substrate proximate and generally outward from the outer sidewalls of the first and second select gate stacks respectively; a common source region is formed in the substrate generally beneath the common source area. A third dielectric layer is disposed over the medial portion of the common source area of the substrate, over the first and second spacers, and over the first and second stacks; a third conductive layer is disposed over a portion of the third dielectric layer which overlies the inner portions of the first and second select gate stacks, the spacers, and the medial portion of the common source area, the third conductive layer forming the common control gate.
One advantage of the present invention is that it provides a process for manufacturing a semiconductor memory device including a pair of memory cells sharing a common source region, wherein the manufacturing process is easily controlled.
The foregoing and other objects, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiment which makes reference to the several figures of the drawing.